1. Field of the Invention
This invention relates to a semiconductor integrated circuit, a layout design method of a semiconductor integrated circuit, and a layout program product of semiconductor integrated circuits.
2. Description of Related Art
Cell-based ICs (integrated circuits) are favorably used in LSI such as ASIC (Application Specific Integrated Circuits), as well as ASSP (Application Specific Standard Products) and microprocessors where high-integration and sophisticated functions are required. Cell-based ICs are designed by combining in-house circuits designed by the user while utilizing a library of cell circuits provided by the semiconductor manufacturer. The cell library includes cells of diverse types and sizes ranging from primitive cells mounted in basic circuits to macro cells containing macros for the CPU and memory, etc. Utilizing these cells reduces the design time and development costs since these cells can be placed and wired on the chip with “placement and routing tools” according to the user's design. Fabricating system LSI is also easy since macro cells containing a circuit layout such as a CPU can be incorporated unchanged onto the chip.
FIG. 1 is a conceptual drawing showing the cell-based IC (Hereafter called chip 1000) of a related art. The chip 1000 contains multiple cells 100, 101. The cells 100, 101 each shall include a diffusion layer 111, 121 for forming MOS transistors. The cell 100 and the cell 101 shall have different circuit structures.
Usually, cells containing different circuits and devices are mounted on the chip. Thus, the layout of the diffusion layer shapes and positions is usually different in each cell. Moreover, the cell internal layout is designed while taking the wiring and installation surface area into account so the distances in the X direction between the diffusion layers in the cell and the cell boundary (Hereafter, called the cell border.) are usually not uniform. In the cell 100 shown in FIG. 1 for example, the distances LD1, LD2 between the diffusion layer 111 and the adjacent cell borders 117, 118 along the X distance and opposite the diffusion layer in the drawing are different values. In cell 101 on the other hand, the distances LD3, LD4 between the diffusion layer 121 and the adjacent cell borders 127, 128 opposite the diffusion layer along the X direction in the drawing are the same values. The longitudinal portion of the gate is set in the Y direction, and the direction perpendicular to that (direction) is set as the X direction.
Distances between the cell border and diffusion layer are also different in each cell due to differences in the layout of each cell. When the cells 100, 101 each possessing different cell structures are placed on the chip 1000 as shown in FIG. 1, then the diffusion layer distances (X direction) between cells are different values due to the type of adjacent cells in the X direction. The distance DS 10 between the diffusion layers 111 of the same type cells 100 for example, is a different value than the distance DS20 between diffusion layer 121 of cell 101 and diffusion layer 111 of cell 100. Moreover, the diffusion layer distance (X direction) between cells is also a different value according to the adjacent cell directions. For example, the distance DS20 to the diffusion layer of cell 100 adjacent to cell border 127 of cell 101, is a different value than the distance DS40 to the diffusion layer of cell 100 adjacent to the cell border 128 of cell 101.
Applying stress to the diffusion layer forming the MOS transistor from the device isolation region when the diffusion layers are isolated for example by STI (Shallow Trench Isolation) is known to change the drive characteristics of that MOS transistor. In the case of a cell 100 containing a diffusion layer 111 forming a MOS transistor, the distances LD1, LD2 between the cell border and diffusion layer 111 are different so that for example even if the adjacent cells are placed at equally spaced distances from each other, the stress acting on the diffusion layer 111 from the cell border side will cause different values on the left and right (along the X direction). The distances DS10-DS40 between the adjacent diffusion layers will therefore be different if multiple MOS transistors are arrayed along the X direction within the cell, so that a MOS transistor at a position that is a distance LD1 from the cell border, and a MOS transistor at a position that is a distance LD2 from the cell border will exhibit different drive characteristics due to the stress from the device isolation region.
Further, when cells 100, 101 are placed as shown in FIG. 1 in a line of mutually adjacent cells 100 in the X direction and a line of adjacent cells 100 and cells 101, the size of the stress acting from the periphery on the diffusion layers 111, 121 will be different values. Also, if there are different type cells within a line, then the diffusion layer distance between cells will not be uniform and the size of the stress applied to the diffusion layers within the cells will be different. Irregularities (variations) will occur within the characteristics of MOS transistors in the chip 1000 and cause the product characteristics to deteriorate.
Along with the greater miniaturization of semiconductor circuits in recent years, fluctuations in MOS transistor characteristics due to differences in stress such as described above are seen as a problem. Technology to equalize the stress applied to the diffusion layer is therefore greatly needed.
Conversely, the technology of the background art as for example in Japanese Laid Open patent Application Publication No. 2006-190727 discloses technology for obtaining the desired performance by making positive use of the stress from the device isolation region. Technology is also disclosed for example in Japanese Laid Open Patent Application Publication No. 2004-241529 for equalizing the stress applied by the channel region of the transistor along the channel width due to trench isolation.
However even applying these technologies to cell-based IC (CBIC) does not correct irregularities in the distance between diffusion layers among cells. The above later Patent document in particular, resolves the problem of stress along the channel width but cannot correct the stress along the channel length or in other words, the direction perpendicular to the gate. The technology of the background art was therefore incapable of preventing fluctuations in MOS transistor characteristics caused by variations in stress on the diffusion layer.